The invention relates generally to semiconductor devices and, more particularly, to semiconductor devices with self-aligned ion implant regions.
Silicon carbide (SiC) is an attractive alternative to silicon for high voltage, high power applications due to SiC's material properties. For example, SiC's wide band gap and high thermal conductivity facilitate elevated temperature operation, and SiC's high electron mobility enables high-speed switching.
For certain devices, such as metal oxide semiconductor field effect transistors (MOSFET), it is desirable to control the channel dimensions. In particular, to achieve a low on-state resistance, it is desirable to reduce the channel width of the device. However, conventional techniques typically employ multiple lithography steps, which introduce overlay misalignments, thereby limiting the resolution of the channel length. For example, for a power MOSFET device, the channel formation typically involves the deposition and patterning of at least two photolithographic layers. For conventional processes, each of the photolithography processes typically incorporates a separate masking layer. Disadvantageously, relying on the alignment of multiple lithography steps to form the channel of a power MOSFET limits the manufacturability of the channel. Specifically, channel dimensions are generally set on the order of 1 micron or greater to account for any misalignments caused by employing multiple lithography processes with multiple masking layers. As a result, SiC MOSFETs are typically designed to have channel lengths sufficiently greater than 1 micron, in order to fall within conventional tolerance limits. These larger channel dimensions disadvantageously increase both the on-state resistance and the power dissipation of the device.
Thus, there is a need to tightly control channel dimensions for SiC MOSFETs. In addition, there is a need to align the gate with the channel. Accordingly, methods for fabricating semiconductor structures are needed to address these issues.